Software | home

top of page

This site was designed with the

website builder. Create your website today.Start Now

To play, press and hold the enter key. To stop, release the enter key.

Example Sketch

Schematic_rtl

FPGA Interconnect Matrix

Hex PIO Buffer

Schematic_bdf

Hardware FSM

Example Sketch

Schematic_rtl

FPGA Interconnect Matrix

Hex PIO Buffer

Schematic_bdf

Hardware FSM

Sketcher V1.1

Using a CycloneV FPGA, Programmable Hardware was configured using the Verilog HDL. The Timers, VGA, SDRAM controller, Address Controller and NIOSII were configured and written in Quartus Prime. The application layer was then written in C using the Eclipse IDE.

To play, press and hold the enter key. To stop, release the enter key.

UART Output

Spidey Sense

UART Output

Spidey Sense

RFD AoA V1.2

The Application Layer and LPS22HB drivers for the Airspeed Transducer were written in Eclipse based IDE's using C and C++ on Si-Labs EFM32WG. Further application layers are being added to add UAVCAN functionality to the device using an STM32 to control the CAN interface.

bottom of page